Field of the Invention
The present invention relates to a semiconductor device comprising a plurality of circuit blocks.
Description of the Related Art
In recent years, semiconductor integrated circuits are required to reduce power dissipation because of a trend toward energy saving considering environmental problems. In general, the power dissipation of a semiconductor integrated circuit formed from logic gates is roughly divided into dynamic power dissipation and static power dissipation.
The dynamic power dissipation is power dissipated by current that charge/discharge a wiring capacitance connected to a logic gate and a gate capacitance at the subsequent stage. The dynamic power dissipation can be reduced by suppressing a signal change. For example, when clock supply to a flip-flop without a signal change is suspended by clock gating, the dynamic power dissipation can be reduced.
On the other hand, the static power dissipation is power dissipated by the leakage current of a transistor in the off state and does not depend on the operating frequency. In general, power dissipation by a junction leakage current, a gate leakage current, a gate-induced drain leakage current, and a subthreshold leakage current are categorized into the static power dissipation.
The static power dissipation by these leakage currents can be suppressed by shutting down power supply (to be referred to as “power shutdown” hereinafter) to some circuit blocks of the semiconductor integrated circuits. When recovering the circuit blocks that have undergone the power shutdown to a normal operation, it is necessary to resume power supply to the circuit block and then perform initialization. Hence, reset is performed before the circuit blocks return to the normal operation.
During the reset operation, since a signal change is actively caused in a storage element such as a flip-flop in each circuit block, clock gating is not performed during the reset operation. For this reason, the power dissipation of the circuit blocks during the reset operation is larger than that in the normal operation.
In the recent semiconductor integrated circuits, the number of power shutdown target regions (to be referred to as “power domains” hereinafter, and for example, circuit blocks) tends to increase. When the plurality of circuit blocks configured to implement the functions of a semiconductor integrated circuit are arranged in different power domains, it is possible to shut down power to power domains where circuit blocks having functions that are not to be used. Unnecessary static power dissipation can thus be reduced.
Each power domain needs the reset operation (especially cancel of the reset signal) after resumption of power supply. In a general semiconductor integrated circuit, when a plurality of circuit blocks are to be reset, the circuit block unit reset operations (reset signal issuance timings or cancel timings) are synchronized to raise the processing efficiency of the entire circuit. Hence, when the reset operations overlap in the plurality of power domains, the power dissipation instantaneously increases during the reset operations.
There is proposed a technique of reducing power dissipation by dividing the frequency of clocks input to circuit blocks and lowering the operating frequency of the circuit blocks during the reset operations. There is also proposed a technique of distributing the degree of increase in power dissipation by inputting clocks to a plurality of circuit blocks at different timings.
However, to complete the reset operations of the circuit blocks, clocks as many as a predetermined number of cycles need to be input. According to the technique of lowering the operating frequency of circuit blocks, the period required for the reset operations becomes long because the operating frequency lowers, although the peak of power dissipation can be reduced to some extent. According to the technique of changing the clock timing, the frequency of clocks input to the circuit blocks is not lowered. However, the period required for the reset operations becomes long as well because the timing of input clocks changes.